1. Field of the Invention
This invention relates generally to computer networking and, more particularly, to the design of a combination USB (Universal Serial Bus)/Ethernet controller device.
2. Description of the Related Art
Various interface standards for connecting computers and external peripherals are in wide use today, each aiming to provide simple connectivity at high speeds. Examples of such standards include the IEEE (Institute of Electrical and Electronics Engineers) 1394 standard also referred to as FireWire, and the Universal Serial Bus (USB), both high-speed serial bus protocols. The most widely used networking standard for connecting computers in both Local Area Networks (LANs) and Wide Area Networks (WANs) has been the Ethernet protocol. More specifically, Ethernet is the IEEE 802.3 series standard, originally based on the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) method that provided a means for two or more computer stations to share a common cabling system. CSMA/CD has formed the basis for Ethernet systems that reached transfer speeds in the megabit range, that is the Mbit/sec range. Recent switched based and/or router based Ethernet systems are capable of supporting transfer rates in the Gbit/sec range. Ethernet generally makes efficient use of shared resources, is typically easy to reconfigure and maintain, and provides compatibility across many manufacturers and systems, while keeping the cost low.
The Ethernet defines a number of wiring and signaling standards for the physical layer (PHY), through means of network access at the Media Access Control (MAC)/Data Link Layer, and through a common addressing format. Above the PHY, Ethernet enabled devices typically communicate by transmitting data packets, which comprise blocks of data that are individually sent and delivered. As with other IEEE 802 LANs, each Ethernet station is given a single 48-bit MAC address, which is used both to specify the destination and the source of each data packet. The MAC data communication protocol sub-layer is a sub-layer of the data link layer specified in the seven-layer OSI (Open System Interconnect) model (layer 2), and acts as an interface between the Logical Link Control (LLC) sub-layer and the network's physical layer. It emulates a full-duplex logical communication channel in a multipoint network to provide addressing and channel access control mechanisms that make it possible for several terminals or network nodes to communicate within a multipoint network, typically a LAN or a WAN.
The Universal Serial Bus (USB) was developed to offer PC users an enhanced and easy-to-use interface for connecting an incredibly diverse range of peripherals to their computers. The development of the USB was initially driven by considerations for laptop computers, which greatly benefit from a small profile peripheral connector. Among the many benefits of the USB is a reduction in the proliferation of cables that can affect even the smallest computer installations. In general, USB has become the interface of choice for PCs because it offers users simple connectivity. USB eliminates the need to have different connectors for printers, keyboards, mice, and other peripherals, and supports a wide variety of data types, from slow mouse inputs to digitized audio and compressed video. In addition, USB devices are hot pluggable, i.e. they can be connected to or disconnected from a PC without requiring the PC to be powered off.
The USB specification has seen various revisions, with the USB 2.0 standard challenging the IEEE 1394 interface (“Firewire”) as the interface of choice for high-speed digital video, among others. With the proliferating design of increasingly smarter, faster, and smaller peripherals, the On-The-Go (OTG) Supplement to the USB 2.0 Specification was developed to address the growing popularity of the portable electronic devices market. Some of the advantages of the USB and OTG include the built-in support in form of more than 1.4 billion USB enabled PCs and peripherals shipped worldwide, smooth and trouble-free experience for the user through a compliance and logo program operated by the USB-IF, a wide variety of USB solutions such as intellectual property (IP) blocks, system-on-chip (SOC) parts, discrete chips, software drivers and systems offered by a large group of industry vendors, and design flexibility based on system needs.
OTG devices typically do not require a PC host, and can communicate directly with each other. For example, a PDA may act as a USB host with the capability to print directly to a USB printer, while also acting as a USB peripheral to communicate with a PC. In general, designers are facing increasing pressure to design smaller and faster products in less time and at lower cost. Concurrently, the introduction of smaller deep sub-micron processes present new challenges, such as integrating the physical layer (PHY—transceiver) analog circuitry required by technologies such as USB and OTG, leading to increased man-hours, fiscal and time investment, and silicon revisions. One way to increase time-to-market while keeping costs low is to provide the PHY in a separate chip. In such a case the designer can typically integrate most of the USB digital logic into the application specific integrated circuit (ASIC) in a small amount of time, and connect to a proven external PHY already available on the market.
Following the release of the USB 2.0 specification, Intel released the USB 2.0 Transceiver Macrocell Interface (UTMI) specification. UTMI defined an interface between two IP blocks, the USB Transceiver Macrocell (IP) and the USB Link layer (SIE). For example, the UTMI can be used to interface between a USB Link and a USB PHY. The signals for a UTMI interface with an 8-bit bi-directional data bus. Typically a minimum of 22 signals is required between the Link and the PHY for a device.
Subsequently, an extension of the original UTMI specification the UTMI+ specification was developed to meet the emerging need of building embedded host and OTG capabilities into USB devices. While the original UTMI specified an interface not meant to couple discrete ICs, the UTMI+ in essence introduced host and On-The-Go capabilities to USB systems. Using UTMI as a starting point, UTMI+ incrementally adds new functionality and interface signals to the Link and PHY. The additional signals total 33 for a full OTG UTMI+ interface. Designers can reuse all blocks from their original UTMI IP, and need only add the new circuits required for host or OTG support. This approach works well for UTMI+, as USB peripherals need only a subset of host and OTG functionality. UTMI+ introduced four levels of functionality, each higher level increasing the complexity required in both hardware and software while remaining completely backward compatible with lower levels.
A Low Pin Interface (LPI) UTMI+ specification, referred to as ULPI, was developed by USB industry leaders in order to provide low-cost USB and OTG PHYs by way of a low-pin, low-cost, small form-factor transceiver interface that may be used by any USB application. Pre-existing specifications, including UTMI and UTMI+ were developed primarily for Macrocell development, and were thus not optimized for use as an external PHY. Building upon the existing UTMI+ specification, the ULPI reduces the number of interface signals to 12 pins, with an optional implementation of 8 pins. As a result, the package size of PHY and Link IC's has generally been reduced, not only lowering the cost of Link and PHY IC's, but also reducing the required size of the associated printed circuit boards (PCBs). Central to the ULPI specification is the LPI, which is in effect a generic bus that defines a clock, three control signals, a bi-directional data bus, and bus arbitration. Typically, a ULPI link will configure the ULPI PHY using register writes on a bi-directional shared data bus. The ULPI PHY is the arbitrator of the 8-bit data bus between the link and the PHY.
Many consumer electronic devices have a USB port. In many instances, however, no Ethernet port is provided on the device, even though the end user may desire such functionality. This is prevalent for products such as game consoles and ultra thin laptops. In such cases, the end user typically has to attach an USB-to-Ethernet controller to one of the available USB ports in order to provide Ethernet functionality to the device. When Ethernet functionality for such devices is desired, it would be more practical to provide Ethernet functionality without having to use up one of a limited number of USB ports. Many solutions to this problem today include an integrated USB hub IC (integrated circuit) and Ethernet controller IC on a single device. Most such solutions are not cost effective and consume considerable power. There is therefore a need for a smaller form factor device, which would consume less power, would be more compact, and would be more convenient for the end user.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.